The present invention relates to a system on a chip (SOC) and, more particularly, to a SOC having a physical interface, such as a DDR interface, and where the SOC is arranged for operation with a superset die having multiple personalities.
SOCs typically include multiple separate logic blocks. Some versions (personalities) of the SOC use all of the logic blocks while other personalities may have one or more blocks disabled or operating at different parameters such as with a slower clock frequency or with narrower or wider busses.
There is an industry-wide drive to reduce design costs for SOC architectures. One area of investigation relates to reduction of the costs relating to the packaging of the SOC die. One way to achieve this is to develop engineering and design techniques allowing improved flexibility, which can be implemented across a broad range of products. Previous efforts have seen a re-ordering of the ball map of the chip along with pad ordering on the die. For instance, one known technique relates to ordering a DDR pad sequence to make the SOC more routing friendly from a board routing perspective. At least two different preferred trace sequences on printed circuit boards for at least one memory device are provided in this technique. A memory controller having a core logic circuit, a plurality of input/output devices and a re-orderer then is provided. The core logic circuit has I/O terminals and each I/O device has a pad. The re-orderer is coupled between the core logic circuit and the I/O devices, and is programmable to selectively connect the input/output devices to the I/O terminals. For example, the re-orderer is programmed to selectively connect a portion of the I/O devices to the I/O terminals such that one of the different preferred trace sequences is substantially supported.
Another area of investigation for cost reduction relates to being able to derive multiple SOCs of high complexity from a single die. To have such flexibility would provide a significant advantage; it would enable the product designer to provide cost-effective solutions depending on varied customer needs. A major challenge in driving the layout for smaller SOCs comes from the physical interface layout such as for large pin count parallel interfaces like the DDR interface.
For a 64-bit physical interface, such as the DDR interface, the traditional method of ordering pads is to keep signals of each byte lane together. The pad order of a typical 64-bit DDR interface is shown in FIG. 1. In FIG. 1, a DDR interface 100 comprises interface pads for a number of byte lanes 102a, 102b, 102c, . . . 102h. The interface pads 104a, 104b, 104c, . . . 104h are, therefore, grouped in groups of eight. For example, the interface pads 104a for byte lane 102a are pads DQ0 to DQ7. The DDR interface 100 also comprises an address/control section 106 for bits 108.
The pads in byte lanes 0 to byte lane 3 routed through the left-hand side of the DDR interface 100 (being to the left-hand side of the address/control pads 106, 108), form a first logical group 110 and the pads in byte lanes 4 to byte lane 7 routed through the right-hand side of the DDR interface 100 (being to the right-hand side of the address/control pads 16. 108) form a second logical group 112.
Now, if the same die is to be repackaged in a smaller package, with, for example, a 32-bit DDR interface SOC, and only half of the interface pads of the DDR physical interface 100 are required, then several options are available for the repackaging. These options include: (1) to bond out byte lanes 0 to 3 (102a-102d) only; (2) to bond out byte lanes 4 to 7 (102e-102h) only; (3) to bond out byte lanes 102c, 102d, 102e and 102f only; and (4) to bond out byte lanes 102a, 102b, 102g and 102h only. As used herein, the term “bond out” means to physically connect with bond wires with a wire bonding process.
These solutions are not without their own problems. For instance, one problem with options (1) and (2) arises at the time of package routing. Bonding out four adjacent byte lanes, and only those four, on one side of the DDR interface 100 may cause significant routing congestion in the corresponding half of the package. This, in turn, can lead to a reduction in signal integrity performance. Similar issues are expected to be encountered for option (3).
So, from these known options, option (4) would seem to be the best choice. This approach is more routing friendly when compared to options (1) to (3), but fresh problems are encountered. If bonding out byte lanes 102a, 102b, 102g and 102h, this means that four byte lanes 102c, 102d, 102e and 102f in the centre region of the DDR interface 100 are left unbonded. As used herein, “unbonded” means not physically connected such as with bond wires. This means that voids are created in that area of the SOC because there are few or no bond wires in those areas. Thus, during a molding process, the flow of mold compound in these voids can cause wire sweep issues, resulting in wire cross-over and shorting. Therefore, to obviate such problems, it is preferable to avoid large voids between wire groups in the SOC.
Thus, it would be advantageous to have a SOC with a physical interface and/or pad ordering method that alleviates the aforementioned problems.